Overview
free

Course Setup and the Incremental Ladder
Why "Wires to Systems"
How to Use This Course
The Incremental Ladder (Step 0 to Step 7)
The Course Lenses
Diagram Legend and Notation Types

Appendix A - Diagram Templates by Step
Appendix B - Technology Mapping Guide
Appendix C - Readiness Assessments
Appendix D - Glossary

Mental Models: Signals, Time, and Abstraction
Signals and Quantities
Analog vs Digital
Time as a First-Class Constraint

Layers of Chip Design
The Layer Stack
Leakage Between Layers
Why You Don't Skip Rungs

Diagramming and Notation
Schematics and Logic Symbols
Timing Diagrams
Block, Bus, and NoC Diagrams
Floorplans and Layout Snippets

Step 0 Circuits: Wires, Components, DC Behavior
Wires, Nodes, Nets
Ohm's Law in Practice
Voltage Dividers and Switching

Step 0 Power Integrity: Power, Ground, and Noise
Power Rails and Ground References
Decoupling and Transients
Noise and Crosstalk Basics

Step 1 Logic Foundations: Levels, Gates, Boolean Algebra
Logic Levels and Thresholds: noise margins, transfer curves, and why "1" and "0" are ranges
Gates as Transfer Functions: AND/OR/NOT and the compositional view of logic networks
Boolean Algebra and Minimization: algebraic reduction and Karnaugh maps as area/timing tools

Step 1 Combinational Blocks: Building Useful Logic
Encoders, Decoders, Multiplexers: selection as a structural pattern for datapaths
Adders and Arithmetic Basics: half/full adders, ripple-carry behavior, and propagation delay as a design constraint
Hazards and Glitches: why correct truth tables can still fail in time, and how to design against spurious transitions

Step 1 Implementation: From Transistors to Standard Cells
CMOS Primitives: inverter, NAND, NOR at the transistor level, and why NAND/NOR dominate libraries
Logic Families and Trade-offs: CMOS vs TTL as an object lesson in power, speed, and interfacing
Standard Cell Libraries: abstraction boundaries, characterization, and why "library choice" shapes feasible timing

Step 2 State Elements: Latches, Flip-Flops, and Clocks
Storage Elements: level-sensitive vs edge-triggered state and how sampling creates discrete time
Setup/Hold and Metastability: why synchronizers exist and what they can and cannot guarantee
Clock Generation and Distribution: clock trees as a physical network with architectural consequences

Step 2 Controllers: FSMs and Control Logic
Moore vs Mealy Machines: output timing, stability, and why the distinction matters for interfaces
State Encoding Strategies: binary vs one-hot vs gray as a trade among area, speed, and verification
From Spec to Verified FSM: designing control from requirements and proving coverage of corner cases

Step 2 Registers and Block Timing Closure
Registers and Register Files: structuring state and understanding read/write timing
Counters, Timers, and Sequencers: building time-based behavior and control rhythms
Critical Paths and Timing Analysis: timing closure "by hand" at block scale and why pipelining is inevitable

Datapath Primitives: ALUs, Shifters, Multipliers
Fast Adders: carry lookahead and carry select as structured shortcuts around ripple delay
Shifts, Compares, and Multiplication: datapath operators and their area/timing/power profiles
Buses and Multiplexing: building datapath connectivity without drowning in wiring

Control Path vs Datapath
Micro-Operations and Control Signals: decomposing instructions into register transfers
Hardwired vs microcoded control: when sequencing is logic and when it is stored control
Microsequencers and formats: how microinstructions represent control intent and constrain datapath design

Building a Simple Processor
Defining a minimal ISA: choosing instructions that make hardware explainable and verifiable
Fetch-Decode-Execute in hardware: wiring the instruction cycle into time and control
Integrating the core: unifying datapath and control into a coherent CPU with testable boundaries

Implementation Paths: FPGA vs ASIC
FPGA mapping: LUTs, block RAM, DSP slices, and what "architecture" means on a programmable fabric
ASIC synthesis: standard cell mapping, constraints, and the cost of committing to silicon
Constraints and trade-offs: timing, area, and power trade space for a simple CPU in each flow

ISA, Microarchitecture, and Pipeline Basics
ISA vs Microarchitecture: what the contract is, and what the implementation is allowed to change
Single-Cycle vs Multi-Cycle: where time goes and how it limits frequency
A Basic Pipeline: the 5-stage mental model and what it optimizes

Pipeline Hazards and Performance
Hazard Taxonomy: data, control, and structural hazards as boundary conflicts
Forwarding and Stalls: paying complexity to buy throughput
Branch Prediction Basics: why speculation exists and what it costs

Memory Interface, MMUs, and Exceptions
Load/Store and Cache-Line Transfers: how memory bandwidth becomes a microarchitectural limiter
Translation and TLBs: virtual memory support as both performance and protection machinery
Interrupts and Exceptions: precise state, context switching implications, and pipeline interaction

Clocking, Timing, and Floorplanning for a Single Core
Clock Trees, Skew, and Jitter: why "clocking" is a distributed system on silicon
Static Timing Analysis: interpreting slack, constraints, and what timing closure proves
Floorplanning the Core: placing caches and I/O, managing wire delay, and aligning physical and logical boundaries

Why Multi-Core Exists
Power and Frequency Limits: why single-core scaling ended and what replaced it
SMP vs Manycore: shared-memory multiprocessors and throughput-oriented designs
Symmetric vs Asymmetric Designs: heterogeneity as a performance and power strategy

On-Chip Interconnect Topologies
Bus, Crossbar, Ring, Mesh: topologies as latency/bandwidth trade-offs
Scalability and Contention: how traffic patterns create hotspots and collapse throughput
QoS and Traffic Classes: fairness, isolation, and real-time constraints on-chip

Cache Coherence Protocols
Coherence Goals and Invariants: what coherence preserves and why it is expensive
Snooping vs Directory: scaling trade-offs and topology interactions
Example Transactions and State Diagrams: walking through coherence events to reason about corner cases

Memory Consistency and Synchronization
Memory Models: strong vs weak ordering and what software can assume
Fences and Atomics: how ordering is enforced in hardware and exposed to compilers
Locks and Advanced Primitives: hardware support for locks, semaphores, and transactional memory

Verification and Validation for Multi-Core
State Explosion: why concurrency makes verification qualitatively harder
Formal vs Simulation: selecting tools that match the failure modes you fear
Post-Silicon Validation: bring-up, debug strategy, and learning from first silicon

What Is an SoC?
SoC Building Blocks: cores, accelerators, memories, and peripheral IP as reusable units
Platform vs Application-Specific SoCs: architectural latitude and ecosystem constraints
IP Reuse and Integration Risk: where integration fails and how boundaries reduce blast radius

On-Chip Networks (NoCs) and System Topology
Bus Fabrics vs Packet NoCs: why scaling forces a networked view
Routing and Flow Control: congestion behavior, buffering, and latency determinism
Virtual Channels and Real-Time: prioritization as an isolation mechanism

Memory Subsystems in SoCs
Caches vs Scratchpads: choosing managed vs explicit locality
DRAM Controllers and PHYs: timing constraints, training, and bandwidth ceilings
Address Spaces and IOMMUs: isolation for devices and coherent integration trade-offs

Peripherals, I/O, and External Interfaces
Peripheral Buses: why on-chip protocols exist and what they optimize for
High-Speed I/O Interfaces: storage, display, camera, and connectivity from a boundary perspective
Pins, SI, and Power: managing pin count, signal integrity, and I/O power budgets

Power, Clock, and Reset Architecture
Power Domains and Gating: turning blocks off safely without breaking system invariants
Clock Domains and CDC: crossings as failure boundaries and the patterns that make them safe
Reset Distribution: sequencing, dependency graphs, and why reset is an integration problem

SoC Design Flow and Integration
Top-Level Integration: IP selection, interface contracts, and system assembly
From RTL to Signoff: synthesis, place-and-route, and closure on timing/power/signal integrity
Tapeout Readiness and Bring-Up: what "ready" means and how first silicon changes your plan

Packaging Fundamentals
Package Types: QFP, BGA, CSP, WLCSP as electrical and manufacturing choices
Thermal, Mechanical, Electrical Constraints: what packages must dissipate, withstand, and preserve
Package PDNs: delivering power through the package and why inductance dominates transient behavior

Chiplets, 2.5D, and 3D Integration
Why Chiplets: yield, modularity, and mixing processes as economic and technical drivers
Interposers, TSVs, and 3D Stacks: what extra dimensions buy you and what they cost
On-Package Interconnects: standards, trade-offs, and modeling latency/bandwidth across dies

High-Speed Links and Off-Chip Interfaces
SerDes and Differential Signaling: encoding, equalization, and the physics behind eye diagrams
Protocol Stacks Over Links: layering, reliability, and what is handled in hardware vs firmware
Channel Modeling and SI Basics: why interconnect modeling is required to hit performance targets

Boards, Systems, and Reference Designs
SoC on PCB: placement, routing, and layer stacks as constraints on signal integrity
Integrating Memory and Power: PDNs on the board, connectors, and system-level stability
Reference Designs: turning an SoC into a reproducible system architecture for products

Reliability, Testing, and Lifetime Concerns
Design for Test: scan chains, BIST, boundary scan, and what they enable post-manufacture
Burn-In and Aging: reliability testing and the mechanisms that cause lifetime drift
Field Failures and Monitoring: resilience strategies, telemetry limits, and feedback into redesign

Pipelining, Parallelism, and Performance Patterns
Parallelism Types: ILP, DLP, and TLP as distinct levers with different costs
Deep vs Shallow Pipelines: frequency, hazards, and verification complexity
Superscalar and Speculation: throughput gains and power/verification consequences
Hardware Acceleration Patterns: vector units, GPUs, and AI accelerators as datapath specialization
Measuring Performance: CPI, bandwidth ceilings, and bottleneck-driven reasoning

Power Management Patterns
Clock Gating: reducing dynamic power without breaking timing assumptions
Power Gating: domain shutdown, retention, and safe sequencing
DVFS: trading frequency/voltage for energy, and the stability limits it introduces
Energy vs Performance Trade-offs: modeling power, performance, and thermal envelopes
Power-Aware Architectures: low-power microarchitecture and SoC-level patterns

Timing, Synchronization, and Clocking Patterns
Useful Skew and Multi-Cycle Paths: intentional timing as a design technique
GALS Systems: globally async, locally sync as a boundary strategy
Synchronizers and CDC Patterns: metastability management and correctness boundaries
FIFOs and Elastic Buffers: rate matching between domains without global timing assumptions
Clock Architecture for Complex Chips: robustness patterns for multi-domain clocks and resets

Security in Hardware Architectures
Secure Boot and Roots of Trust: establishing an initial trusted state
Trusted Execution and Isolation: privilege, enclaves, and what hardware can enforce
Secure Debug and Lifecycle: provisioning, debug access control, and decommissioning
Side-Channels: leakage sources and architecture-level mitigations
Fault Injection and Robustness: threat models, detection, and hardening trade-offs

Verification, Validation, and Tool Flows
Simulation, Emulation, Formal, Prototyping: choosing the right tool for the failure mode
Coverage and Closure: what it means to "finish" verification and why it is never absolute
Toolchain Overview: HDL entry, synthesis, place-and-route, signoff, and where each can break assumptions
Constraints and Signoff Thinking: timing, power, SI, and DRC/LVS as distinct closure criteria
Post-Silicon Validation Loops: bring-up, debug instrumentation, and learning cycles back into design

/wires-to-systems/wires-to-systems

A Basic Pipeline: the 5-stage mental model and what it optimizes

Sign in to access this lesson.

Sign in Create account