Wires to Systems

From Simple Circuits to SoCs and Multi-Die Systems

42 modules

181 lessons

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Part 1

Course Setup and the Incremental Ladder

Course Setup and the Incremental LadderSign in
Why "Wires to Systems"Sign in
How to Use This CourseSign in
The Incremental Ladder (Step 0 to Step 7)Sign in
The Course LensesSign in
Diagram Legend and Notation TypesSign in

Part 2

General

Appendix A - Diagram Templates by StepSign in
Appendix B - Technology Mapping GuideSign in
Appendix C - Readiness AssessmentsSign in
Appendix D - GlossarySign in

Part 3

Mental Models: Signals, Time, and Abstraction

Mental Models: Signals, Time, and AbstractionSign in
Signals and QuantitiesSign in
Analog vs DigitalSign in
Time as a First-Class ConstraintSign in

Part 4

Layers of Chip Design

Layers of Chip DesignSign in
The Layer StackSign in
Leakage Between LayersSign in
Why You Don't Skip RungsSign in

Part 5

Diagramming and Notation

Diagramming and NotationSign in
Schematics and Logic SymbolsSign in
Timing DiagramsSign in
Block, Bus, and NoC DiagramsSign in
Floorplans and Layout SnippetsSign in

Part 6

Step 0 Circuits: Wires, Components, DC Behavior

Step 0 Circuits: Wires, Components, DC BehaviorSign in
Wires, Nodes, NetsSign in
Ohm's Law in PracticeSign in
Voltage Dividers and SwitchingSign in

Part 7

Step 0 Power Integrity: Power, Ground, and Noise

Step 0 Power Integrity: Power, Ground, and NoiseSign in
Power Rails and Ground ReferencesSign in
Decoupling and TransientsSign in
Noise and Crosstalk BasicsSign in

Part 8

Step 1 Logic Foundations: Levels, Gates, Boolean Algebra

Step 1 Logic Foundations: Levels, Gates, Boolean AlgebraSign in
Logic Levels and Thresholds: noise margins, transfer curves, and why "1" and "0" are rangesSign in
Gates as Transfer Functions: AND/OR/NOT and the compositional view of logic networksSign in
Boolean Algebra and Minimization: algebraic reduction and Karnaugh maps as area/timing toolsSign in

Part 9

Step 1 Combinational Blocks: Building Useful Logic

Step 1 Combinational Blocks: Building Useful LogicSign in
Encoders, Decoders, Multiplexers: selection as a structural pattern for datapathsSign in
Adders and Arithmetic Basics: half/full adders, ripple-carry behavior, and propagation delay as a design constraintSign in
Hazards and Glitches: why correct truth tables can still fail in time, and how to design against spurious transitionsSign in

Part 10

Step 1 Implementation: From Transistors to Standard Cells

Step 1 Implementation: From Transistors to Standard CellsSign in
CMOS Primitives: inverter, NAND, NOR at the transistor level, and why NAND/NOR dominate librariesSign in
Logic Families and Trade-offs: CMOS vs TTL as an object lesson in power, speed, and interfacingSign in
Standard Cell Libraries: abstraction boundaries, characterization, and why "library choice" shapes feasible timingSign in

Part 11

Step 2 State Elements: Latches, Flip-Flops, and Clocks

Step 2 State Elements: Latches, Flip-Flops, and ClocksSign in
Storage Elements: level-sensitive vs edge-triggered state and how sampling creates discrete timeSign in
Setup/Hold and Metastability: why synchronizers exist and what they can and cannot guaranteeSign in
Clock Generation and Distribution: clock trees as a physical network with architectural consequencesSign in

Part 12

Step 2 Controllers: FSMs and Control Logic

Step 2 Controllers: FSMs and Control LogicSign in
Moore vs Mealy Machines: output timing, stability, and why the distinction matters for interfacesSign in
State Encoding Strategies: binary vs one-hot vs gray as a trade among area, speed, and verificationSign in
From Spec to Verified FSM: designing control from requirements and proving coverage of corner casesSign in

Part 13

Step 2 Registers and Block Timing Closure

Step 2 Registers and Block Timing ClosureSign in
Registers and Register Files: structuring state and understanding read/write timingSign in
Counters, Timers, and Sequencers: building time-based behavior and control rhythmsSign in
Critical Paths and Timing Analysis: timing closure "by hand" at block scale and why pipelining is inevitableSign in

Part 14

Datapath Primitives: ALUs, Shifters, Multipliers

Datapath Primitives: ALUs, Shifters, MultipliersSign in
Fast Adders: carry lookahead and carry select as structured shortcuts around ripple delaySign in
Shifts, Compares, and Multiplication: datapath operators and their area/timing/power profilesSign in
Buses and Multiplexing: building datapath connectivity without drowning in wiringSign in

Part 15

Control Path vs Datapath

Control Path vs DatapathSign in
Micro-Operations and Control Signals: decomposing instructions into register transfersSign in
Hardwired vs microcoded control: when sequencing is logic and when it is stored controlSign in
Microsequencers and formats: how microinstructions represent control intent and constrain datapath designSign in

Part 16

Building a Simple Processor

Building a Simple ProcessorSign in
Defining a minimal ISA: choosing instructions that make hardware explainable and verifiableSign in
Fetch-Decode-Execute in hardware: wiring the instruction cycle into time and controlSign in
Integrating the core: unifying datapath and control into a coherent CPU with testable boundariesSign in

Part 17

Implementation Paths: FPGA vs ASIC

Implementation Paths: FPGA vs ASICSign in
FPGA mapping: LUTs, block RAM, DSP slices, and what "architecture" means on a programmable fabricSign in
ASIC synthesis: standard cell mapping, constraints, and the cost of committing to siliconSign in
Constraints and trade-offs: timing, area, and power trade space for a simple CPU in each flowSign in

Part 18

ISA, Microarchitecture, and Pipeline Basics

ISA, Microarchitecture, and Pipeline BasicsSign in
ISA vs Microarchitecture: what the contract is, and what the implementation is allowed to changeSign in
Single-Cycle vs Multi-Cycle: where time goes and how it limits frequencySign in
A Basic Pipeline: the 5-stage mental model and what it optimizesSign in

Part 19

Pipeline Hazards and Performance

Pipeline Hazards and PerformanceSign in
Hazard Taxonomy: data, control, and structural hazards as boundary conflictsSign in
Forwarding and Stalls: paying complexity to buy throughputSign in
Branch Prediction Basics: why speculation exists and what it costsSign in

Part 20

Memory Interface, MMUs, and Exceptions

Memory Interface, MMUs, and ExceptionsSign in
Load/Store and Cache-Line Transfers: how memory bandwidth becomes a microarchitectural limiterSign in
Translation and TLBs: virtual memory support as both performance and protection machinerySign in
Interrupts and Exceptions: precise state, context switching implications, and pipeline interactionSign in

Part 21

Clocking, Timing, and Floorplanning for a Single Core

Clocking, Timing, and Floorplanning for a Single CoreSign in
Clock Trees, Skew, and Jitter: why "clocking" is a distributed system on siliconSign in
Static Timing Analysis: interpreting slack, constraints, and what timing closure provesSign in
Floorplanning the Core: placing caches and I/O, managing wire delay, and aligning physical and logical boundariesSign in

Part 22

Why Multi-Core Exists

Why Multi-Core ExistsSign in
Power and Frequency Limits: why single-core scaling ended and what replaced itSign in
SMP vs Manycore: shared-memory multiprocessors and throughput-oriented designsSign in
Symmetric vs Asymmetric Designs: heterogeneity as a performance and power strategySign in

Part 23

On-Chip Interconnect Topologies

On-Chip Interconnect TopologiesSign in
Bus, Crossbar, Ring, Mesh: topologies as latency/bandwidth trade-offsSign in
Scalability and Contention: how traffic patterns create hotspots and collapse throughputSign in
QoS and Traffic Classes: fairness, isolation, and real-time constraints on-chipSign in

Part 24

Cache Coherence Protocols

Cache Coherence ProtocolsSign in
Coherence Goals and Invariants: what coherence preserves and why it is expensiveSign in
Snooping vs Directory: scaling trade-offs and topology interactionsSign in
Example Transactions and State Diagrams: walking through coherence events to reason about corner casesSign in

Part 25

Memory Consistency and Synchronization

Memory Consistency and SynchronizationSign in
Memory Models: strong vs weak ordering and what software can assumeSign in
Fences and Atomics: how ordering is enforced in hardware and exposed to compilersSign in
Locks and Advanced Primitives: hardware support for locks, semaphores, and transactional memorySign in

Part 26

Verification and Validation for Multi-Core

Verification and Validation for Multi-CoreSign in
State Explosion: why concurrency makes verification qualitatively harderSign in
Formal vs Simulation: selecting tools that match the failure modes you fearSign in
Post-Silicon Validation: bring-up, debug strategy, and learning from first siliconSign in

Part 27

What Is an SoC?

What Is an SoC?Sign in
SoC Building Blocks: cores, accelerators, memories, and peripheral IP as reusable unitsSign in
Platform vs Application-Specific SoCs: architectural latitude and ecosystem constraintsSign in
IP Reuse and Integration Risk: where integration fails and how boundaries reduce blast radiusSign in

Part 28

On-Chip Networks (NoCs) and System Topology

On-Chip Networks (NoCs) and System TopologySign in
Bus Fabrics vs Packet NoCs: why scaling forces a networked viewSign in
Routing and Flow Control: congestion behavior, buffering, and latency determinismSign in
Virtual Channels and Real-Time: prioritization as an isolation mechanismSign in

Part 29

Memory Subsystems in SoCs

Memory Subsystems in SoCsSign in
Caches vs Scratchpads: choosing managed vs explicit localitySign in
DRAM Controllers and PHYs: timing constraints, training, and bandwidth ceilingsSign in
Address Spaces and IOMMUs: isolation for devices and coherent integration trade-offsSign in

Part 30

Peripherals, I/O, and External Interfaces

Peripherals, I/O, and External InterfacesSign in
Peripheral Buses: why on-chip protocols exist and what they optimize forSign in
High-Speed I/O Interfaces: storage, display, camera, and connectivity from a boundary perspectiveSign in
Pins, SI, and Power: managing pin count, signal integrity, and I/O power budgetsSign in

Part 31

Power, Clock, and Reset Architecture

Power, Clock, and Reset ArchitectureSign in
Power Domains and Gating: turning blocks off safely without breaking system invariantsSign in
Clock Domains and CDC: crossings as failure boundaries and the patterns that make them safeSign in
Reset Distribution: sequencing, dependency graphs, and why reset is an integration problemSign in

Part 32

SoC Design Flow and Integration

SoC Design Flow and IntegrationSign in
Top-Level Integration: IP selection, interface contracts, and system assemblySign in
From RTL to Signoff: synthesis, place-and-route, and closure on timing/power/signal integritySign in
Tapeout Readiness and Bring-Up: what "ready" means and how first silicon changes your planSign in

Part 33

Packaging Fundamentals

Packaging FundamentalsSign in
Package Types: QFP, BGA, CSP, WLCSP as electrical and manufacturing choicesSign in
Thermal, Mechanical, Electrical Constraints: what packages must dissipate, withstand, and preserveSign in
Package PDNs: delivering power through the package and why inductance dominates transient behaviorSign in

Part 34

Chiplets, 2.5D, and 3D Integration

Chiplets, 2.5D, and 3D IntegrationSign in
Why Chiplets: yield, modularity, and mixing processes as economic and technical driversSign in
Interposers, TSVs, and 3D Stacks: what extra dimensions buy you and what they costSign in
On-Package Interconnects: standards, trade-offs, and modeling latency/bandwidth across diesSign in

Part 35

High-Speed Links and Off-Chip Interfaces

High-Speed Links and Off-Chip InterfacesSign in
SerDes and Differential Signaling: encoding, equalization, and the physics behind eye diagramsSign in
Protocol Stacks Over Links: layering, reliability, and what is handled in hardware vs firmwareSign in
Channel Modeling and SI Basics: why interconnect modeling is required to hit performance targetsSign in

Part 36

Boards, Systems, and Reference Designs

Boards, Systems, and Reference DesignsSign in
SoC on PCB: placement, routing, and layer stacks as constraints on signal integritySign in
Integrating Memory and Power: PDNs on the board, connectors, and system-level stabilitySign in
Reference Designs: turning an SoC into a reproducible system architecture for productsSign in

Part 37

Reliability, Testing, and Lifetime Concerns

Reliability, Testing, and Lifetime ConcernsSign in
Design for Test: scan chains, BIST, boundary scan, and what they enable post-manufactureSign in
Burn-In and Aging: reliability testing and the mechanisms that cause lifetime driftSign in
Field Failures and Monitoring: resilience strategies, telemetry limits, and feedback into redesignSign in

Part 38

Pipelining, Parallelism, and Performance Patterns

Pipelining, Parallelism, and Performance PatternsSign in
Parallelism Types: ILP, DLP, and TLP as distinct levers with different costsSign in
Deep vs Shallow Pipelines: frequency, hazards, and verification complexitySign in
Superscalar and Speculation: throughput gains and power/verification consequencesSign in
Hardware Acceleration Patterns: vector units, GPUs, and AI accelerators as datapath specializationSign in
Measuring Performance: CPI, bandwidth ceilings, and bottleneck-driven reasoningSign in

Part 39

Power Management Patterns

Power Management PatternsSign in
Clock Gating: reducing dynamic power without breaking timing assumptionsSign in
Power Gating: domain shutdown, retention, and safe sequencingSign in
DVFS: trading frequency/voltage for energy, and the stability limits it introducesSign in
Energy vs Performance Trade-offs: modeling power, performance, and thermal envelopesSign in
Power-Aware Architectures: low-power microarchitecture and SoC-level patternsSign in

Part 40

Timing, Synchronization, and Clocking Patterns

Timing, Synchronization, and Clocking PatternsSign in
Useful Skew and Multi-Cycle Paths: intentional timing as a design techniqueSign in
GALS Systems: globally async, locally sync as a boundary strategySign in
Synchronizers and CDC Patterns: metastability management and correctness boundariesSign in
FIFOs and Elastic Buffers: rate matching between domains without global timing assumptionsSign in
Clock Architecture for Complex Chips: robustness patterns for multi-domain clocks and resetsSign in

Part 41

Security in Hardware Architectures

Security in Hardware ArchitecturesSign in
Secure Boot and Roots of Trust: establishing an initial trusted stateSign in
Trusted Execution and Isolation: privilege, enclaves, and what hardware can enforceSign in
Secure Debug and Lifecycle: provisioning, debug access control, and decommissioningSign in
Side-Channels: leakage sources and architecture-level mitigationsSign in
Fault Injection and Robustness: threat models, detection, and hardening trade-offsSign in

Part 42

Verification, Validation, and Tool Flows

Verification, Validation, and Tool FlowsSign in
Simulation, Emulation, Formal, Prototyping: choosing the right tool for the failure modeSign in
Coverage and Closure: what it means to "finish" verification and why it is never absoluteSign in
Toolchain Overview: HDL entry, synthesis, place-and-route, signoff, and where each can break assumptionsSign in
Constraints and Signoff Thinking: timing, power, SI, and DRC/LVS as distinct closure criteriaSign in
Post-Silicon Validation Loops: bring-up, debug instrumentation, and learning cycles back into designSign in

Course overview