Bits to Devices

How to Design Embedded Systems

49 modules

199 lessons

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Start the course

Part 1

Course Setup and the Incremental Ladder

Course Setup and the Incremental LadderSign in
Why "Bits to Devices"Sign in
How to Use This CourseSign in
The Incremental Ladder (Step 0 -> Step 7)Sign in
The Course LensesSign in
Diagram Legend and Notation TypesSign in

Part 2

What Is an Embedded System?

What Is an Embedded System?Sign in
Embedded vs General-Purpose Computing: constraints, failure costs, and correctnessSign in
The triad: hardware, firmware, environmentSign in
Range of systems: tiny MCUs to embedded Linux, and why the ladder still appliesSign in

Part 3

Digital Logic Basics

Digital Logic BasicsSign in
Logic Gates and Boolean ReasoningSign in
Sequential Logic and StateSign in
Timing as a ConstraintSign in

Part 4

From Datapaths to Simple CPUs

From Datapaths to Simple CPUsSign in
ALU, Registers, Control Unit: A Minimal CPU BoundarySign in
Fetch-Decode-Execute: Instruction Execution as a Timing MachineSign in
Minimal Instruction Sets: Expressiveness Under BoundariesSign in

Part 5

Microcontrollers vs Microprocessors vs SoCs

Microcontrollers vs Microprocessors vs SoCsSign in
What "Microcontroller" Implies: Integration as an Architectural CommitmentSign in
Typical MCU Block Diagram: Where Bottlenecks HideSign in
Choosing Under Constraints: Power, Cost, I/O, and Performance as Coupled AxesSign in

Part 6

Diagramming Embedded Architectures

Diagramming Embedded ArchitecturesSign in
System Block Diagrams: MCU, Power, Sensors, Actuators, and Failure DomainsSign in
Timing Diagrams: Buses, Signals, and Control-Loop Timing as the Real SpecificationSign in
Memory and Register Maps: Address Space as a Contract Between Silicon and FirmwareSign in

Part 7

Building Blocks of Control Logic

Building Blocks of Control LogicSign in
Decoders and Multiplexers: Selection and Routing as Control LogicSign in
Synchronous Design and Clocking: Making Time a ContractSign in
Hazards, Setup/Hold, and Metastability: When Timing Contracts BreakSign in

Part 8

Bus Interfaces and Simple On-Chip Interconnects

Bus Interfaces and Simple On-Chip InterconnectsSign in
Internal Buses - Shared Wires, Shared LatencySign in
Address, Data, and Control Signals - How Buses Carry MeaningSign in
Arbitration Intuition - Turning Contention into WaitingSign in

Part 9

Instruction Sets and Assembly Basics

Instruction Sets and Assembly BasicsSign in
Registers, Formats, Addressing Modes - The CPU Programming ContractSign in
Load/Store IntuitionSign in
Control Flow in AssemblySign in

Part 10

Firmware Toolchain and Build Process

Firmware Toolchain and Build ProcessSign in
From C to Machine CodeSign in
Linker Scripts and Memory PlacementSign in
Flashing and ProgrammingSign in

Part 11

Startup Code and Reset Sequences

Startup Code and Reset SequencesSign in
Reset Vector and Startup RoutinesSign in
Stack and Heap SetupSign in
Main Loop as Firmware TopSign in

Part 12

Debugging at the Bare-Metal Level

Debugging at the Bare-Metal LevelSign in
JTAG/SWD and Debug ProbesSign in
Breakpoints, Watchpoints, and Memory InspectionSign in
Logging Channels and Their Architectural CostsSign in

Part 13

Memory Types and Organization

Memory Types and OrganizationSign in
Flash, SRAM, EEPROM, External Memory: what each is good for and what it costsSign in
Sections and Layout: code, data, stack, heap and why layout choices are correctness choicesSign in
Addressing and Maps: reading memory maps as architectural documentationSign in

Part 14

Clocking and Timing Sources

Clocking and Timing SourcesSign in
Oscillators and Crystals: accuracy, drift, and why timekeeping affects protocols and controlSign in
PLLs and Clock Trees (Conceptual): distributing time and creating new failure modes via skewSign in
Performance vs Power: configuring clocks as a resource allocation decisionSign in

Part 15

Timers and Timekeeping

Timers and TimekeepingSign in
Timer Peripherals: compare/capture as the base of periodic behaviorSign in
System Tick Timers: creating a time base for schedulingSign in
Time as a Shared Dependency: what breaks when different subsystems assume different clocksSign in

Part 16

Latency, Jitter, and Real-Time Constraints

Latency, Jitter, and Real-Time ConstraintsSign in
Worst-Case vs Average Timing: designing for bounds rather than hopesSign in
Interrupt latency and service time: why fast enough needs measurement and budgetingSign in
Jitter impacts: control stability and communication reliability as downstream consequencesSign in

Part 17

Power and Energy Constraints

Power and Energy ConstraintsSign in
Sleep Modes and Power States: power as a state machine with wake-up costsSign in
DVFS Concepts (High Level): trading speed for energy and what timing it destabilizesSign in
Battery and Thermal Limits: designing around finite energy and heat dissipation budgetsSign in

Part 18

GPIO, Polling, and Basic Interfacing

GPIO, Polling, and Basic InterfacingSign in
Pin Configuration: input/output, pull-ups/pull-downs and electrical intentSign in
Polling vs Interrupt-Driven I/O: choosing based on latency budgets and CPU availabilitySign in
Debouncing and Basic Robustness: turning noisy physical signals into stable eventsSign in

Part 19

Interrupts and ISRs

Interrupts and ISRsSign in
Vectors and priorities: how the core chooses what happens nextSign in
ISR safety: minimal work, bounded time, and predictable shared-state rulesSign in
Shared data hazards: races, reentrancy, and patterns for correctness under preemptionSign in

Part 20

Serial Interfaces: UART, SPI, I²C

Serial Interfaces: UART, SPI, I²CSign in
UART framing and baud rates: timing agreements as protocol requirementsSign in
SPI semantics: clock polarity/phase, full-duplex behavior, and chip-select realitiesSign in
I2C semantics: addressing, start/stop, ACK/NACK and bus-level failure behaviorSign in

Part 21

Field Buses and Industrial Interfaces

Field Buses and Industrial InterfacesSign in
CAN/CAN-FD basics: arbitration, framing and why it fits safety-adjacent systemsSign in
RS-485-style multi-drop: electrical and protocol implications of shared linesSign in
Ecosystem view: automotive/industrial buses as layered stacks with tooling expectationsSign in

Part 22

Analog Interfaces: ADC and DAC

Analog Interfaces: ADC and DACSign in
Sampling and quantization: resolution, rates, and what you lose at the boundarySign in
References, noise, filtering: designing measurement chains rather than reading "numbers"Sign in
DACs and PWM outputs: producing controlled actuation signals and managing artifactsSign in

Part 23

Sensors, Actuators, and Simple Control Loops

Sensors, Actuators, and Simple Control LoopsSign in
Sensor interfacing patterns: temperature, pressure, IMU style devices and calibration realitiesSign in
Actuation patterns: motors, relays, solenoids and safety constraints on outputsSign in
Closed-loop vs open-loop: PID intuition and mapping control requirements to hardware limitsSign in

Part 24

Superloops and Cooperative Scheduling

Superloops and Cooperative SchedulingSign in
The superloop model: one main loop polling tasks and why it's still commonSign in
Task decomposition: structuring work so deadlines are visibleSign in
Pros and cons: predictability and simplicity versus starvation and latency cliffsSign in

Part 25

Periodic and Aperiodic Tasks

Periodic and Aperiodic TasksSign in
Sampling vs event-driven tasks: mapping work to time or interruptsSign in
Rate monotonic intuition (high level): why shorter periods usually need higher prioritySign in
Designing for determinism: budgeting, bounding, and measuring execution timeSign in

Part 26

Control Loops and Sampling Theory (High Level)

Control Loops and Sampling Theory (High Level)Sign in
Sampling rate and aliasing: what you must assume to trust measurementsSign in
Proportional and PID controllers: stability intuition and tuning constraintsSign in
Requirements to capabilities: matching loop rates and latency to MCU and peripheral realitiesSign in

Part 27

Scheduling with Interrupts and Timers

Scheduling with Interrupts and TimersSign in
Timer-driven periodic work: triggering loops and sampling at precise intervalsSign in
Mixing polling and interrupts: composing mechanisms without losing predictabilitySign in
Priority and preemption without an RTOS: failure modes and disciplined design rulesSign in

Part 28

Real-Time Design Patterns

Real-Time Design PatternsSign in
Deadline-based thinking: treating time as a correctness conditionSign in
Watchdogs in control systems: coupling liveness detection to safety behaviorSign in
Overruns and degraded modes: designing safe fallback behavior when deadlines are missedSign in

Part 29

RTOS Concepts and Primitives

RTOS Concepts and PrimitivesSign in
Tasks, Priorities, Ready Queues: what an RTOS schedules and whySign in
Mutexes, Semaphores, Queues, Events: coordination primitives and their timing costsSign in
Scheduling Policies: priority-based and round-robin behavior as predictable machinerySign in

Part 30

RTOS vs Bare-Metal: Choosing an Approach

RTOS vs Bare-Metal: Choosing an ApproachSign in
When a Superloop Is Enough: keeping complexity low while meeting deadlinesSign in
When You Need an RTOS: integration, concurrency, and timing complexity thresholdsSign in
Hybrid Patterns: RTOS for orchestration, bare-metal for tight timing regionsSign in

Part 31

Interrupt Handling in RTOS Systems

Interrupt Handling in RTOS SystemsSign in
ISR Design With RTOS APIs: what is safe to call and why restrictions existSign in
Deferred Work: splitting ISR fast paths from worker-task slow pathsSign in
Priority Inversion: how it happens and mitigation patternsSign in

Part 32

Memory Management and Isolation

Memory Management and IsolationSign in
Static vs Dynamic Allocation: determinism, fragmentation, and lifecycle correctnessSign in
Heap Safety Under Real Time: when allocation becomes a timing hazardSign in
MMU/MPU Concepts: isolation, fault containment, and where MCUs can enforce boundariesSign in

Part 33

Concurrency Hazards and Patterns

Concurrency Hazards and PatternsSign in
Races, Deadlocks, Inversions: failure modes in small systems with big consequencesSign in
Minimal-Lock and Lock-Free Intuition: reducing shared state to reduce timing riskSign in
Testing Concurrent Firmware: verification strategies under resource constraintsSign in

Part 34

Fault Models and Failure Modes

Fault Models and Failure ModesSign in
Hardware Faults: transient upsets, EMI/EMC issues and component wearSign in
Software Faults: hangs, memory corruption, and logic bugs as safety eventsSign in
Environmental Conditions: temperature, vibration, moisture and designing to specSign in

Part 35

Defensive Programming in Embedded Systems

Defensive Programming in Embedded SystemsSign in
Input Validation and Sanity Checks: treating sensor input as adversarial or wrongSign in
Assertions vs Fail-Safe: choosing failure behavior that protects people and devicesSign in
Degraded Modes: operating safely when parts of the system are unreliableSign in

Part 36

Watchdogs, Brown-Out, and Reset Strategies

Watchdogs, Brown-Out, and Reset StrategiesSign in
Watchdog Correctness: designing "petting" patterns that actually detect hangsSign in
Brown-Out and Safe Reset: handling low power without corrupting stateSign in
Boot-Time Self-Tests: startup diagnostics and safe bring-up behaviorSign in

Part 37

Redundancy, Diagnostics, and Health Monitoring

Redundancy, Diagnostics, and Health MonitoringSign in
Redundant Sensing and Actuation (High Level): N+1 and voting intuition and what it costsSign in
BIST and Periodic Diagnostics: catching degradation before it becomes failureSign in
Telemetry and Field Logging: error codes, logs, and fleet observability for devicesSign in

Part 38

Functional Safety and Certification Context

Functional Safety and Certification ContextSign in
Safety Integrity Ideas (Conceptual): what certification tries to bound and why process mattersSign in
Fail-Safe vs Fail-Operational: architectural choices and their implications for redundancySign in
Documentation and Traceability: linking requirements to tests as an engineering disciplineSign in

Part 39

Hardware–Software Partitioning

Hardware–Software PartitioningSign in
Partitioning Rules: what belongs in hardware, firmware, or external modules and whySign in
Peripherals vs Bit-Banging: cost, timing, and reliability trade-offsSign in
Designing for Total Cost: performance, BOM, power, and maintainability togetherSign in

Part 40

Board-Level Design Considerations

Board-Level Design ConsiderationsSign in
Power Delivery and Decoupling: stable power as a correctness prerequisiteSign in
Clocking and Signal Integrity Basics: why board realities leak into firmware timingSign in
Connectors and Protection: ESD, transient protection, and survivabilitySign in

Part 41

Bootloaders, Update Mechanisms, and Security

Bootloaders, Update Mechanisms, and SecuritySign in
Bootloader Responsibilities: startup, recovery, and update orchestrationSign in
Fail-Safe Updates and Rollback: designing update flows that survive power lossSign in
Secure Boot Intuition: signed firmware, trust roots, and limiting downgrade attacksSign in

Part 42

Manufacturing, Test, and Calibration

Manufacturing, Test, and CalibrationSign in
Design for Test: test points, fixtures, and factory modesSign in
Factory programming and calibration: making accuracy and identity reproducibleSign in
Provisioning and configuration: serial numbers, configuration, and key injection boundariesSign in

Part 43

System Integration and End-to-End Architecture

System Integration and End-to-End ArchitectureSign in
Device to Gateway to Cloud (Conceptual): boundaries and failure propagation across tiersSign in
Fleet Diagnostics: remote telemetry, updates, and management responsibilitiesSign in
Reference Architectures: sensor nodes, motor controllers, consumer devices and their dominant constraintsSign in

Part 44

Product Lifecycle and Maintenance

Product Lifecycle and MaintenanceSign in
Field Updates and Bug Fixes: operational discipline across long-lived hardwareSign in
Hardware Revisions: compatibility, migration, and supporting multiple variantsSign in
End-of-Life Planning: sunsetting devices without breaking dependent systemsSign in

Part 45

Embedded Design Patterns

Embedded Design PatternsSign in
State Machines and Event Loops: structuring behavior under timing constraintsSign in
Driver and Command Abstractions: isolating peripheral details from application logicSign in
HAL vs Direct Register Access: portability versus determinism and controlSign in

Part 46

Control, Sensing, and Actuation Patterns

Control, Sensing, and Actuation PatternsSign in
Sensor fusion (conceptual): combining noisy measurements and handling driftSign in
Motor control patterns (basic): control structure without deep power electronicsSign in
Safety interlocks: permissioning outputs and enforcing invariants on actuatorsSign in

Part 47

Test, Simulation, and Emulation

Test, Simulation, and EmulationSign in
Unit and integration testing for firmware: isolating logic without losing timing realismSign in
Simulators and emulators: shifting discovery earlier and understanding what they cannot modelSign in
Hardware-in-the-loop (conceptual): closing the loop with real signals and controlled environmentsSign in

Part 48

Design Checklists for New Embedded Devices

Design Checklists for New Embedded DevicesSign in
Requirements and constraints: timing, power, environment, safety as up-front architecture inputsSign in
MCU and peripheral selection: I/O needs, memory budgets, and expansion plansSign in
Firmware architecture and test plan: update strategy, diagnostic plan, and verification scopeSign in

Part 49

Appendices and Reference Materials

Appendices and Reference MaterialsSign in
Appendix A - Diagram templates by stepSign in
Appendix B - Mapping to real-world platformsSign in
Appendix C - Readiness checklists (ladder gates)Sign in
Appendix D - Glossary (canonical terms)Sign in

Course overview