Overview
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Course Setup and the Incremental Ladder
Why "Bits to Devices"
How to Use This Course
The Incremental Ladder (Step 0 -> Step 7)
The Course Lenses
Diagram Legend and Notation Types

What Is an Embedded System?
Embedded vs General-Purpose Computing: constraints, failure costs, and correctness
The triad: hardware, firmware, environment
Range of systems: tiny MCUs to embedded Linux, and why the ladder still applies

Digital Logic Basics
Logic Gates and Boolean Reasoning
Sequential Logic and State
Timing as a Constraint

From Datapaths to Simple CPUs
ALU, Registers, Control Unit: A Minimal CPU Boundary
Fetch-Decode-Execute: Instruction Execution as a Timing Machine
Minimal Instruction Sets: Expressiveness Under Boundaries

Microcontrollers vs Microprocessors vs SoCs
What "Microcontroller" Implies: Integration as an Architectural Commitment
Typical MCU Block Diagram: Where Bottlenecks Hide
Choosing Under Constraints: Power, Cost, I/O, and Performance as Coupled Axes

Diagramming Embedded Architectures
System Block Diagrams: MCU, Power, Sensors, Actuators, and Failure Domains
Timing Diagrams: Buses, Signals, and Control-Loop Timing as the Real Specification
Memory and Register Maps: Address Space as a Contract Between Silicon and Firmware

Building Blocks of Control Logic
Decoders and Multiplexers: Selection and Routing as Control Logic
Synchronous Design and Clocking: Making Time a Contract
Hazards, Setup/Hold, and Metastability: When Timing Contracts Break

Bus Interfaces and Simple On-Chip Interconnects
Internal Buses - Shared Wires, Shared Latency
Address, Data, and Control Signals - How Buses Carry Meaning
Arbitration Intuition - Turning Contention into Waiting

Instruction Sets and Assembly Basics
Registers, Formats, Addressing Modes - The CPU Programming Contract
Load/Store Intuition
Control Flow in Assembly

Firmware Toolchain and Build Process
From C to Machine Code
Linker Scripts and Memory Placement
Flashing and Programming

Startup Code and Reset Sequences
Reset Vector and Startup Routines
Stack and Heap Setup
Main Loop as Firmware Top

Debugging at the Bare-Metal Level
JTAG/SWD and Debug Probes
Breakpoints, Watchpoints, and Memory Inspection
Logging Channels and Their Architectural Costs

Memory Types and Organization
Flash, SRAM, EEPROM, External Memory: what each is good for and what it costs
Sections and Layout: code, data, stack, heap and why layout choices are correctness choices
Addressing and Maps: reading memory maps as architectural documentation

Clocking and Timing Sources
Oscillators and Crystals: accuracy, drift, and why timekeeping affects protocols and control
PLLs and Clock Trees (Conceptual): distributing time and creating new failure modes via skew
Performance vs Power: configuring clocks as a resource allocation decision

Timers and Timekeeping
Timer Peripherals: compare/capture as the base of periodic behavior
System Tick Timers: creating a time base for scheduling
Time as a Shared Dependency: what breaks when different subsystems assume different clocks

Latency, Jitter, and Real-Time Constraints
Worst-Case vs Average Timing: designing for bounds rather than hopes
Interrupt latency and service time: why fast enough needs measurement and budgeting
Jitter impacts: control stability and communication reliability as downstream consequences

Power and Energy Constraints
Sleep Modes and Power States: power as a state machine with wake-up costs
DVFS Concepts (High Level): trading speed for energy and what timing it destabilizes
Battery and Thermal Limits: designing around finite energy and heat dissipation budgets

GPIO, Polling, and Basic Interfacing
Pin Configuration: input/output, pull-ups/pull-downs and electrical intent
Polling vs Interrupt-Driven I/O: choosing based on latency budgets and CPU availability
Debouncing and Basic Robustness: turning noisy physical signals into stable events

Interrupts and ISRs
Vectors and priorities: how the core chooses what happens next
ISR safety: minimal work, bounded time, and predictable shared-state rules
Shared data hazards: races, reentrancy, and patterns for correctness under preemption

Serial Interfaces: UART, SPI, I²C
UART framing and baud rates: timing agreements as protocol requirements
SPI semantics: clock polarity/phase, full-duplex behavior, and chip-select realities
I2C semantics: addressing, start/stop, ACK/NACK and bus-level failure behavior

Field Buses and Industrial Interfaces
CAN/CAN-FD basics: arbitration, framing and why it fits safety-adjacent systems
RS-485-style multi-drop: electrical and protocol implications of shared lines
Ecosystem view: automotive/industrial buses as layered stacks with tooling expectations

Analog Interfaces: ADC and DAC
Sampling and quantization: resolution, rates, and what you lose at the boundary
References, noise, filtering: designing measurement chains rather than reading "numbers"
DACs and PWM outputs: producing controlled actuation signals and managing artifacts

Sensors, Actuators, and Simple Control Loops
Sensor interfacing patterns: temperature, pressure, IMU style devices and calibration realities
Actuation patterns: motors, relays, solenoids and safety constraints on outputs
Closed-loop vs open-loop: PID intuition and mapping control requirements to hardware limits

Superloops and Cooperative Scheduling
The superloop model: one main loop polling tasks and why it's still common
Task decomposition: structuring work so deadlines are visible
Pros and cons: predictability and simplicity versus starvation and latency cliffs

Periodic and Aperiodic Tasks
Sampling vs event-driven tasks: mapping work to time or interrupts
Rate monotonic intuition (high level): why shorter periods usually need higher priority
Designing for determinism: budgeting, bounding, and measuring execution time

Control Loops and Sampling Theory (High Level)
Sampling rate and aliasing: what you must assume to trust measurements
Proportional and PID controllers: stability intuition and tuning constraints
Requirements to capabilities: matching loop rates and latency to MCU and peripheral realities

Scheduling with Interrupts and Timers
Timer-driven periodic work: triggering loops and sampling at precise intervals
Mixing polling and interrupts: composing mechanisms without losing predictability
Priority and preemption without an RTOS: failure modes and disciplined design rules

Real-Time Design Patterns
Deadline-based thinking: treating time as a correctness condition
Watchdogs in control systems: coupling liveness detection to safety behavior
Overruns and degraded modes: designing safe fallback behavior when deadlines are missed

RTOS Concepts and Primitives
Tasks, Priorities, Ready Queues: what an RTOS schedules and why
Mutexes, Semaphores, Queues, Events: coordination primitives and their timing costs
Scheduling Policies: priority-based and round-robin behavior as predictable machinery

RTOS vs Bare-Metal: Choosing an Approach
When a Superloop Is Enough: keeping complexity low while meeting deadlines
When You Need an RTOS: integration, concurrency, and timing complexity thresholds
Hybrid Patterns: RTOS for orchestration, bare-metal for tight timing regions

Interrupt Handling in RTOS Systems
ISR Design With RTOS APIs: what is safe to call and why restrictions exist
Deferred Work: splitting ISR fast paths from worker-task slow paths
Priority Inversion: how it happens and mitigation patterns

Memory Management and Isolation
Static vs Dynamic Allocation: determinism, fragmentation, and lifecycle correctness
Heap Safety Under Real Time: when allocation becomes a timing hazard
MMU/MPU Concepts: isolation, fault containment, and where MCUs can enforce boundaries

Concurrency Hazards and Patterns
Races, Deadlocks, Inversions: failure modes in small systems with big consequences
Minimal-Lock and Lock-Free Intuition: reducing shared state to reduce timing risk
Testing Concurrent Firmware: verification strategies under resource constraints

Fault Models and Failure Modes
Hardware Faults: transient upsets, EMI/EMC issues and component wear
Software Faults: hangs, memory corruption, and logic bugs as safety events
Environmental Conditions: temperature, vibration, moisture and designing to spec

Defensive Programming in Embedded Systems
Input Validation and Sanity Checks: treating sensor input as adversarial or wrong
Assertions vs Fail-Safe: choosing failure behavior that protects people and devices
Degraded Modes: operating safely when parts of the system are unreliable

Watchdogs, Brown-Out, and Reset Strategies
Watchdog Correctness: designing "petting" patterns that actually detect hangs
Brown-Out and Safe Reset: handling low power without corrupting state
Boot-Time Self-Tests: startup diagnostics and safe bring-up behavior

Redundancy, Diagnostics, and Health Monitoring
Redundant Sensing and Actuation (High Level): N+1 and voting intuition and what it costs
BIST and Periodic Diagnostics: catching degradation before it becomes failure
Telemetry and Field Logging: error codes, logs, and fleet observability for devices

Functional Safety and Certification Context
Safety Integrity Ideas (Conceptual): what certification tries to bound and why process matters
Fail-Safe vs Fail-Operational: architectural choices and their implications for redundancy
Documentation and Traceability: linking requirements to tests as an engineering discipline

Hardware–Software Partitioning
Partitioning Rules: what belongs in hardware, firmware, or external modules and why
Peripherals vs Bit-Banging: cost, timing, and reliability trade-offs
Designing for Total Cost: performance, BOM, power, and maintainability together

Board-Level Design Considerations
Power Delivery and Decoupling: stable power as a correctness prerequisite
Clocking and Signal Integrity Basics: why board realities leak into firmware timing
Connectors and Protection: ESD, transient protection, and survivability

Bootloaders, Update Mechanisms, and Security
Bootloader Responsibilities: startup, recovery, and update orchestration
Fail-Safe Updates and Rollback: designing update flows that survive power loss
Secure Boot Intuition: signed firmware, trust roots, and limiting downgrade attacks

Manufacturing, Test, and Calibration
Design for Test: test points, fixtures, and factory modes
Factory programming and calibration: making accuracy and identity reproducible
Provisioning and configuration: serial numbers, configuration, and key injection boundaries

System Integration and End-to-End Architecture
Device to Gateway to Cloud (Conceptual): boundaries and failure propagation across tiers
Fleet Diagnostics: remote telemetry, updates, and management responsibilities
Reference Architectures: sensor nodes, motor controllers, consumer devices and their dominant constraints

Product Lifecycle and Maintenance
Field Updates and Bug Fixes: operational discipline across long-lived hardware
Hardware Revisions: compatibility, migration, and supporting multiple variants
End-of-Life Planning: sunsetting devices without breaking dependent systems

Embedded Design Patterns
State Machines and Event Loops: structuring behavior under timing constraints
Driver and Command Abstractions: isolating peripheral details from application logic
HAL vs Direct Register Access: portability versus determinism and control

Control, Sensing, and Actuation Patterns
Sensor fusion (conceptual): combining noisy measurements and handling drift
Motor control patterns (basic): control structure without deep power electronics
Safety interlocks: permissioning outputs and enforcing invariants on actuators

Test, Simulation, and Emulation
Unit and integration testing for firmware: isolating logic without losing timing realism
Simulators and emulators: shifting discovery earlier and understanding what they cannot model
Hardware-in-the-loop (conceptual): closing the loop with real signals and controlled environments

Design Checklists for New Embedded Devices
Requirements and constraints: timing, power, environment, safety as up-front architecture inputs
MCU and peripheral selection: I/O needs, memory budgets, and expansion plans
Firmware architecture and test plan: update strategy, diagnostic plan, and verification scope

Appendices and Reference Materials
Appendix A - Diagram templates by step
Appendix B - Mapping to real-world platforms
Appendix C - Readiness checklists (ladder gates)
Appendix D - Glossary (canonical terms)

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PLLs and Clock Trees (Conceptual): distributing time and creating new failure modes via skew

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